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Patent Searching and Data


Title:
MANUFACTURE OF SEMICONDUCTOR NONVOLATILE MEMORY
Document Type and Number:
Japanese Patent JPS59222962
Kind Code:
A
Abstract:

PURPOSE: To form a high concentration region in a channel region with high accuracy, to shape a thin select gate insulating film having high quality easily and to change a PACMOS memory into low program voltage by implanting ions into the high concentration region through a gate insulating film and a polycrystalline silicon film formed on the gate insulating film.

CONSTITUTION: A floating gate electrode 4 consisting of polycrystalline silicon is formed, and the electrode 4 is oxidized. A thin polycrystalline silicon film 11 is shaped so as to coat a channel L1. A high concentration region 7 is formed through ion implantation while using the floating gate electrode 4, a side-surface oxide film 9' for the floating gate electorde 4 and the side surface of the thin polycrystalline silicon film 11 as masks. The high concentration region 7 is shaped so as not to be infiltrated into a second channel region L2 by properly selecting the thickness of the thin polycrystalline silicon film 11 and the acceleration energy of ion implantation. Consequently, a sharp potential gap can be obtained on a boundary between the channel L1 and the channel L2 in the surfaces of the channels on a program. Accordingly, the rate of generation of hot electrons is increased, and program voltage is lowered.


Inventors:
KAMIYA MASAAKI
KOJIMA YOSHIKAZU
Application Number:
JP9719283A
Publication Date:
December 14, 1984
Filing Date:
June 01, 1983
Export Citation:
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Assignee:
SEIKO INSTR & ELECTRONICS
International Classes:
H01L21/8247; H01L29/788; H01L29/792; (IPC1-7): H01L29/78
Attorney, Agent or Firm:
Keinosuke Hayashi