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Patent Searching and Data


Title:
MANUFACTURE OF SEMICONDUCTOR PACKAGE
Document Type and Number:
Japanese Patent JPH1041436
Kind Code:
A
Abstract:

To enable the application of electroless Au-plating for manufacturing multilayered semiconductor package in excellent PCT resistance and high reli ability by forming a multilayered electric insulating layer using thermosetting polyphenylene ether resin, containing no glass cloth.

In order to improve the bonding properties onto an electric insulating layer 20, base processing 15 such as chemical processing, etc., is performed on the surface of the electric insulating layer 20 on a metallic plate 10. Next, the electric insulating layer 20 is formed using a thermosetting polyphenylene ether resin of high thermal resistant at Tg value of 180°C and absorption rate of at most 0.05% excluding a glass cloth. Through these processes, the chemical resistance and the humidity resistance for providing the required insulating property under a specific humidity environment are improved. Accordingly, the application of electrodless Au-plating is made possible, thereby a multilayered a semiconductor package in excellent PCT resistance and high reliability can be obtained.


Inventors:
KOMATSU TAKATSUGU
Application Number:
JP22578696A
Publication Date:
February 13, 1998
Filing Date:
July 24, 1996
Export Citation:
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Assignee:
NIPPON MICRON KK
International Classes:
H05K1/05; H01L23/12; H01L23/14; (IPC1-7): H01L23/14; H01L23/12; H05K1/05