To provide plural matched filters by a small circuit scale.
Input signals from a signal input terminal 11 are successively sampled and held in sample-and-hold circuits SH#, 1#'-SH# and 2561#'. The output of the sample-and-hold circuits SH#, 1#'-SH# and 256#' is inputted to multipliers 14#, 1#'-14# and 2561t' and the multipliers 17#, 1#'-17# and 256#'. In the multipliers 14#, 1#'-14# arid 256#' respective multiplication with the first PN code of # and 256#' chips from a PN code register 13 is executed and a correlation arithmetic result to the first PN code is outputted from an adder 15. In the multipliers 17#, 1#'-17# and 256#', multiplication with the output of the respective stages of the PN code register 16 where the second PN code of 4 chips is repeatedly stored is executed. Through multiplexers 20#, 1#'-20# and 256#' controlled by an addition control register 18, the multiplied results of the adders 17#, 1#'-17# and 256#' for 4 chips are added in the adder 21 and correlation to the second PN code is outputted.
SHU TERUHEI
SUZUKI KUNIHIKO
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