Title:
抵抗素子を含む数理問題解法回路
Document Type and Number:
Japanese Patent JP7345859
Kind Code:
B2
Abstract:
It is described a mathematical solving circuit (100) comprising: a crosspoint matrix (MG) including a plurality of row conductors (Li), a plurality of column conductors (Cj) and a plurality of analog resistive memories (Gij), each connected between a row conductor and a column conductor; a plurality of operational amplifiers (OAi) each having: a first input terminal (IN1i) connected to a respective row conductor (Li), a second input terminal (IN2i) connected to a ground terminal (GR) at least one operational amplifier (OAi) of the plurality being such to take the respective first input terminal (IN1i) to a virtual ground.
More Like This:
| WO/2005/015383 | SWITCHED CHARGE MULTIPLIER-DIVIDER |
Inventors:
Yermini, Daniele
Sun, Zhong
Pedretti, Giacomo
Sun, Zhong
Pedretti, Giacomo
Application Number:
JP2020517172A
Publication Date:
September 19, 2023
Filing Date:
September 27, 2018
Export Citation:
Assignee:
POLITECNICO DI MILANO
International Classes:
G06G7/16; G06G7/32; G06G7/60; G11C11/54; G11C13/00
Foreign References:
| WO2017052598A1 | ||||
| WO2016068953A1 | ||||
| US20170040054 |
Other References:
村野 靖,『オペアンプ回路の「しくみ」と「基本」』,第1版,株式会社技術評論社 片岡 巌,2012年12月10日,第117頁
Attorney, Agent or Firm:
▲吉▼川 俊雄
Hiroshi Ichikawa
Hiroshi Ichikawa
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