Title:
MEMORY ARRAY CHIP
Document Type and Number:
Japanese Patent JPS60245275
Kind Code:
A
Abstract:
@ An on-chip timing control apparatus (19) for generation of timing signals for a large scale integrated (LSI) chip or semiconductor memory array (12) is disclosed. This apparatus requires only an off-chip trigger pulse input (16) and it may be used both during the production testing of the memory and during normal functional operation. In the testing environment it allows use of much less expensive peripheral test equipment, while also providing for much greater accuracy in determination of whether or not the memory array meets its timing specification. Use during normal functional operation (subsequent to use in the test environment) provides for a guarantee of defect free operation.
Inventors:
KLARA WALTER S (US)
KWAP THEODORE W (US)
MARCELLO VICTOR (US)
RASMUSSEN ROBERT A (US)
KWAP THEODORE W (US)
MARCELLO VICTOR (US)
RASMUSSEN ROBERT A (US)
Application Number:
JP604585A
Publication Date:
December 05, 1985
Filing Date:
January 18, 1985
Export Citation:
Assignee:
IBM
International Classes:
G11C29/00; G01R31/26; G01R31/28; G11C7/00; G11C7/22; G11C11/401; G11C11/407; G11C29/14; G11C29/50; G11C29/56; H01L21/66; H01L21/822; H01L27/04; H01L27/10; (IPC1-7): G01R31/26; G11C7/00; G11C29/00; H01L21/66; H01L27/10
Domestic Patent References:
| JPS5755598A | 1982-04-02 | |||
| JPS53117342A | 1978-10-13 | |||
| JPS5435052A | 1979-03-14 |
Attorney, Agent or Firm:
Next student Okada