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Title:
SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JPS60245276
Kind Code:
A
Abstract:

PURPOSE: To enable the improvement in carrier mobility of a diffused layer, e.g. fT of a bi-polar transistor and in operating speed by a method wherein a diffused layer and an active region are formed so as to make each of the two contain only susceptors or doners.

CONSTITUTION: After a P type impurity is selectively ion-implanted to an epitaxial layer 4 in the part serving as the base region, a P type base region 7 is formed by heat-treatment. A groove 13 is formed down to a desired emitter depth in the base region 7. An N+ type region 8 of high concentration is formed only in the groove 13 by growing single crystal Si containing a high concentration of N type impurity. This manner enables the formation of the emitter region 8 only with donars and leads the electric impurity concentration in the emitter region 8 to a required emitter-impurity-concentration without an increase in chemical impurity concentration. Therefore, the chemical impurity concentration decreases, and the mobility in the emitter region 8 and fT of the transistor increase, resulting in speed-up in switching action.


Inventors:
TANEOKA TADAYUKI
Application Number:
JP10046284A
Publication Date:
December 05, 1985
Filing Date:
May 21, 1984
Export Citation:
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Assignee:
HITACHI LTD
International Classes:
H01L29/73; H01L21/331; H01L29/08; H01L29/732; (IPC1-7): H01L29/72
Attorney, Agent or Firm:
Akio Takahashi



 
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