To provide a memory control circuit which prevents an unstable state of a data strobe signal from being propagated to an internal circuit, while using an existing circuit as much as possible.

The memory control circuit has a first delay circuit 220 delaying an input data strobe signal by first delay quantity, a second delay circuit 230 delaying an input data strobe signal by second delay quantity larger than the first delay quantity, an AND circuit 240 in which the first delay signal delayed by the first delay circuit 220 and the second delay signal delayed by the second delay circuit 230 are input and third delay signal DQS 3 including a rise edge being synchronous with a trailing edge of the data strobe signal is generated, a flip-flop 260 taking-in first data D1 input in response to the first delay signal, and a flip-flop 280 taking-in second data D2 input in response to the third delay signal DQS 3.

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