PURPOSE: To make the operation of a high speed logic integrated circuit device including the flip-flop and of a computer system or the like stable by preventing malfunction of the flip-flop DEFF with data enable.

CONSTITUTION: A data selection circuit DSL delivering a noninverting output signal Q of a slave mater latch SML or input data D to a data input terminal DI of the slave master latch SML selectively is provided to a pre-stage of the slave master latch SML whose state is transited synchronously with a trailing edge of a clock signal CKB. Then a logic level of a data enable signal DAB is changed synchronously with the leading edge of the clock signal CKB.