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Title:
METHOD AND APPARATUS FOR BONDING
Document Type and Number:
Japanese Patent JPH1050760
Kind Code:
A
Abstract:

To provide a method and an apparatus for bonding semiconductor chips capable of high-reliability bonding, without troublesome operation etc., even in the case of narrow-pitched inner leads.

In the case of bonding a group of electrode bumps provided on one principal surface of a semiconductor chip 8 to a group or inner leads 10' corresponding, the inner leads and the electrodes bumps corresponding are positioned collating their positional relationship, and both are joined after that, on the basis of design value co-ordinates of the inner leads and the co-ordinate information of the chip electrodes inputted beforehand. Besides, the above- mentioned bonding apparatus is provided with a memory 14 capable of inputting the co-ordinates of design values of line inner leads 10' and the co-ordinate information of the electrode bumps of the chip 8, and has a stage driving mechanism 7 which co-ordinate-collates the positional relationship of the inner leads 10' and the electrode bumps corresponding, causes X, Y, and θ of a semiconductor chip stage 6 to operate, and positions the inner leads and electrode bumps corresponding, a co-ordinate lighting means 15, and a driving mechanism control system 16 as well.


Inventors:
NAKAO MITSUHIRO
Application Number:
JP20359496A
Publication Date:
February 20, 1998
Filing Date:
August 01, 1996
Export Citation:
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Assignee:
TOSHIBA CORP
International Classes:
H01L21/60; (IPC1-7): H01L21/60
Attorney, Agent or Firm:
Suyama Saichi