Title:
METHOD FOR CORRECTING ARITHMETIC ERROR OF ANALOG ARITHMETIC CIRCUIT, AND FILTER CIRCUIT
Document Type and Number:
Japanese Patent JP3527076
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To correct an arithmetic error in an analog arithmetic circuit.
SOLUTION: An analog input signal Ain is sampled for every sampling cycle, and successively transferred to sample and hold circuits 110-11N-1 constituted of analog arithmetic circuits serially connected in N stages. The output of each sample and hold circuit is multiplied by coefficient data stored in a coefficient register 20 in analog/digital multiplying circuits 310-31N-1, and the multiplied result of each tap is added by an adder 40 constituted of an analog arithmetic circuit. Data for correcting the arithmetic error of analog arithmetic circuit are reflected in the coefficient data in the multiplying circuits 310-31N-1 so that the arithmetic error can be corrected.
Inventors:
Suzuki, Kunihiko
Shu, Nagaaki
Shu, Nagaaki
Application Number:
JP28426497A
Publication Date:
May 17, 2004
Filing Date:
October 02, 1997
Export Citation:
Assignee:
TAKATORI IKUEIKAI:KK
International Classes:
G06G7/12; G06G7/16; H03H15/00; (IPC1-7): G06G7/16; G06G7/12
Attorney, Agent or Firm:
高橋 英生 （外１名）
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