PURPOSE: To facilitate time delay adjustments by providing a time delay generating means which guarantees the delay time difference between a primary clock signal and a master clock signal on a master clock output line within a specific time range.
CONSTITUTION: The master clock signal distributed to master clock output lines is supplied to a circuit through a line 140. The circuit has serial programmable delay blocks connected to respective clock outputs and for the signal sent to the 1st programmable delay block 138, a fuse circuit 160 selects which of inputs 147 and 149 is sent out from the output 150 of a multiplexer 148 and outputs it. Namely, when a fuse 166 is not disconnected, the multiplexer 148 outputs the clock signal from an inverter 142 after it is delayed by 8 gates. When the fuse 166 is blown by applying a sufficient current to a terminal 162, the multiplexer 148 outputs the undelayed master clock signal.
ROBAATO ENU DEMINGU
UIRIAMU SHII TERERU
DEIBITSUDO DABURIYUU HETSUJIZU
