To provide a method for manufacturing an integrated circuit package such as a BGA package to be used with an integrated circuit chip.

An integrated circuit package has a substrate including a cavity where a lower conductivity level in a package is exposed, and thus, in order to reduce the number of through-holes formed in the substrate, junctions can be formed between the integrated circuit chip and the conductivity level. As a result, an additional signal line interconnection part can be built in a board circuit package and/or the integrated circuit chip can be made small. Thus, an electric performance can be improved. When there are a plurality of wire bonding layers in the substrate, a spacing between wires becomes long and therefore a wire bonding process and the following sealing process can be easily carried out.