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Patent Searching and Data


Title:
METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JP2003158235
Kind Code:
A
Abstract:

To provide a method of manufacturing semiconductor device by which visual inspections performed on soldered junctions are made easily, because no burr is produced and cut end faces of leads are also plated, and, in addition, joining strengths are also increased.

This method of manufacturing semiconductor device includes a first step of forming a plurality of unit lead frames 11, on each of which an element mounting section 12 and many leads 13 are arranged, in a conductive plate 10 in a matrix-like state and a second step of batch sealing the semiconductor element mounting sides of the lead frames 11 with a resin after semiconductor elements 16 are respectively mounted on the element mounting sections 12 and necessary electrical connection is performed. This method also includes a third step of dividing the resin-sealed intermediate product into semiconductor devices 21 respectively provided with the semiconductor elements 16 by sizing the product 20 and a fourth step of removing burrs 22 produced by the sizing by bringing the semiconductor devices 21 into contact with each other while vibrating and/or stirring the devices 21 and, at the same time, plating the exposed portions of the lead frames 11.


Inventors:
YASUNAGA HISASHI
NARIMATSU HIROAKI
FUKUI ATSUSHI
Application Number:
JP2001354753A
Publication Date:
May 30, 2003
Filing Date:
November 20, 2001
Export Citation:
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Assignee:
MITSUI HIGH TEC
International Classes:
C25D7/12; H01L21/48; H01L23/31; H01L23/50; H01L23/495; (IPC1-7): H01L23/50; C25D7/12
Attorney, Agent or Firm:
Nakamae Fujio