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Title:
METHOD FOR MANUFACTURING SEMICONDUCTOR SUBSTRATE, SEMICONDUCTOR SUBSTRATE, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JP2014060391
Kind Code:
A
Abstract:

To provide a technique for forming an MOS structure having a small EOT without increasing an interface trap density.

A method for manufacturing a semiconductor substrate which comprises: a semiconductor crystal layer; an intermediate layer composed of an oxide, nitride, or oxynitride of a semiconductor crystal constituting the semiconductor crystal layer; and a first insulating layer composed of an oxide and in which the semiconductor crystal layer, the intermediate layer, and the first insulating layer are located in this order comprises the steps of: (a) forming a first insulating layer on an original semiconductor crystal layer; and (b) forming an intermediate layer by nitriding or oxidizing a part of the original semiconductor crystal layer or making a part of the original semiconductor crystal layer oxynitride by exposing a surface of the first insulating layer to nitrogen plasma and forming a semiconductor crystal layer which is a remainder of the original semiconductor crystal layer.


Inventors:
TAKENAKA MITSURU
TAKAGI SHINICHI
HAN JAEHOON
TAKADA TOMOYUKI
OSADA TAKENORI
HATA MASAHIKO
Application Number:
JP2013171759A
Publication Date:
April 03, 2014
Filing Date:
August 21, 2013
Export Citation:
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Assignee:
SUMITOMO CHEMICAL CO
UNIV TOKYO
International Classes:
H01L21/316; H01L21/318; H01L21/336; H01L29/78; H01L29/786
Attorney, Agent or Firm:
Longhua International Patent Service Corporation
Shigenori Hayashi