METHOD OF PLANALIZING SEMICONDUCTOR WAFER, AND PLANALIZING DEVICE

Title:

METHOD OF PLANALIZING SEMICONDUCTOR WAFER, AND PLANALIZING DEVICE

Document Type and Number:

Japanese Patent JP3847500

Kind Code:

B2

Abstract:

PROBLEM TO BE SOLVED: To enhance the uniformity of the amount of processing on a wafer, especially, in the inner area and the periphery of the wafer, while keeping high processing efficiency, concerning the planalizing technique of the surface pattern of the wafer used in the manufacturing process of a semiconductor integrated circuit.
SOLUTION: A wafer is processed offsetting, frictions being produced by making a plurality of polishing tools movable in independent direction on the wafer at the same time.

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Inventors:

Yasui feeling
Soichi Katagiri
Masahiko Sato

Application Number:

JP28768299A

Publication Date:

November 22, 2006

Filing Date:

October 08, 1999

Export Citation:

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Assignee:

株式会社日立製作所

International Classes:

B24B21/04; H01L21/304; B24B37/005; B24B37/07; (IPC1-7): H01L21/304; B24B21/04; B24B37/00; B24B37/04

Domestic Patent References:

JP10230451A
JP6008133A
JP10256201A
JP8195364A
JP10335276A
JP11207577A

Attorney, Agent or Firm:

Nitto International Patent Office
Katsuo Ogawa
Yasuo Sakuta

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