Title:
2層拡散バリアーを析出させる方法
Document Type and Number:
Japanese Patent JP3779161
Kind Code:
B2
Abstract:
A method for depositing a two-layer diffusion barrier on a semiconductor wafer consisting of a TaN layer and a Ta layer serving as a carrier layer for copper interconnects. The TaN layer is inventively deposited at temperatures above 200° C. in a first step, and the Ta layer is deposited in a second step while cooling the semiconductor wafer to a temperature below 50° C.
Inventors:
Schmidbauer, Sven
Roof, alexander
Roof, alexander
Application Number:
JP2000619017A
Publication Date:
May 24, 2006
Filing Date:
May 17, 2000
Export Citation:
Assignee:
Infineon Technologies AG
International Classes:
C23C14/06; H01L21/285; H01L21/28; H01L21/768
Domestic Patent References:
| JP2002543282A | ||||
| JP9017790A | ||||
| JP9120991A | ||||
| JP9162293A | ||||
| JP9186157A | ||||
| JP11074227A | ||||
| JP11260824A | ||||
| JP2000208519A |
Attorney, Agent or Firm:
Kenzo Hara International Patent Office
Kenzo Hara
Ryuichi Kijima
Toru Enya
Ichiro Kaneko
Kenzo Hara
Ryuichi Kijima
Toru Enya
Ichiro Kaneko
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