Title:
結合トランスリニア・ループにおいて除去可能特異点を摂動する方法および回路
Document Type and Number:
Japanese Patent JP4323337
Kind Code:
B2
Abstract:
A translinear network (34) has first (Q1, Q2, Q3, Q4) and second (Q4, Q3, Q5, Q6) translinear loops. A Trafton-Hastings clamp circuit (36) is connected to generate a piecewise-polynomial-continuous current IY, the value of which becomes undefined when current IX=0 due to a removable singularity in the transfer equation at this point. A current mirror (38) comprising a plurality of transistors (M1, M2, M3) is coupled to the Trafton-Hastings clamp circuit (36), and operates to add additional currents in transistors Q3 and Q5 to IX, when the Trafton-Hastings clamp transistor (Q7) conducts, so as to perturb the removable singularity in the transfer equation into the left half-plane.
Inventors:
Roy Ay, Hastings
Application Number:
JP2004021461A
Publication Date:
September 02, 2009
Filing Date:
January 29, 2004
Export Citation:
Assignee:
Texas Instruments Incorporated
International Classes:
H03F3/343; G06G7/16; G06G7/20; H03F1/26
Foreign References:
| US5134355 | ||||
| US20020180526 | ||||
| US4323797 | ||||
| US6074082 |
Other References:
Alan Hastings,Integrated MOSFET interface for a synchronously-rectified SMPS,Bipolar/BiCMOS Circuits and Technology Meeting, 1995., Proceedings of the 1995,米国,IEEE,1995年10月 2日,p. 58-61
Attorney, Agent or Firm:
Hideto Asamura
Hajime Asamura
Hayashi Zouzo
Eiichi Sobue
Hajime Asamura
Hayashi Zouzo
Eiichi Sobue