PURPOSE: To use a digital processor with a peripheral equipment having a variable access time without decreasing the basic clock frequency of a microprocessor, that is, without adding a microprocessor waiting state.

CONSTITUTION: Normally, a clock pulse is connected with a microprocessor 11 which can perform access to memory devices 13 and 14 having different access time by a clock circuit 12. The access to the 'low speed' memory device 14 is detected by the pertinent clock circuit, and at least one clock pulse is not connected with the pertinent microprocessor in response to it. The operation in the proper amounts of the pertinent microprocessor is delayed so that the pertinent microprocessor can read the effective data from the pertinent slow memory device. The number of clock pulses whose arrival at the pertinent microprocessor is interrupted can be set by a certain delaying circuit in the pertinent clock circuit.