PURPOSE: To reduce the number of steps of memory access and a program and to accelerate processing to execute a semaphore.

CONSTITUTION: This microprocessor is comprised of an instruction decoder 2 which outputs a conditional operand write signal when a conditional operand write arithmetic instruction is decoded, a computing element 4 which computes operand data according to the decoded result of the instruction at the instruction decoder 2, a flag register 5 on which the conditional flag of a computed result at the computing element 4 is set, an AND gate 6 which outputs a prohibition signal to prohibit the operand data write of the computed result based on the content of the conditional flag set on the flag register 5 and the conditional operand write signal outputted from the decoder 2, and an operand write control unit 7 which prohibitively controls the operand data write of the computed result according to the prohibition signal outputted from the AND gate 6.