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Title:
MICROPROGRAM DEBUGGING SYSTEM
Document Type and Number:
Japanese Patent JPH05158735
Kind Code:
A
Abstract:

PURPOSE: To accumulate the trace information on many steps end to use them with the small memory capacity by accumulating the information on only the selected necessary addresses not the information on all executed addresses.

CONSTITUTION: The information is fetched by a register (1) 5 of the input side and then shifted to a register (2) 6 of the 2nd stage. The difference between both registers 5 and 6 is equal to 1 when 8 program is successively carried out. This difference is decided by a +1 adder circuit 8 and a comparator circuit 7. The deciding result of the comparator 7 is inputted to a write control. circuit 12. The circuit 12 performs no writing operation to a storage element 11 when the program is successively carried out based on the deciding result of the comparator 7. Then the circuit 12 writes an unbranched address and a branched address into the element 11 when the executing order is changed by a branch instruction, etc. Furthermore, an execution start address, etc., are also stored in the element 11. Then the data are read out of the element 11 by a processor 10 contained in a debug back-up device for interpolation of the continuous addresses and then outputted to a display device 9.


Inventors:
MORI KENJI
Application Number:
JP32287591A
Publication Date:
June 25, 1993
Filing Date:
December 06, 1991
Export Citation:
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Assignee:
HITACHI LTD
International Classes:
G06F11/28; (IPC1-7): G06F11/28
Attorney, Agent or Firm:
Ogawa Katsuo



 
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