To shorten the man-hours of setting to reduce design costs, and to maintain and improve the design quality of a single chip as a whole.
A digital output cell(M) expressing the output circuit part of a logic part (71) is arranged in a corresponding analog circuit part (72), an analog circuit part for verification including a logic part in a pseudo-status is prepared, and the operation of the analog circuit part for verification is verified by an analog analyzing tool. Thus, since man-hours related to the conventional transfer of data can be reduced, design man-hours are shortened and design cost is reduced. Also, since the analog circuit part for verification including the logic part in a pseudo-status is verified by the analog analyzing tool, the design quality of a single chip as a whole can be maintained or improved.
YAMATANI TETSUHISA
KANEKO SHINICHI
Satoshi Kono
Makoto Nakamura
Kurata Masatoshi
Takashi Mine
Yoshihiro Fukuhara
Sadao Muramatsu
Ryo Hashimoto