Title:
MOS CAPACITOR AND MANUFACTURE
Document Type and Number:
Japanese Patent JP3392595
Kind Code:
B2
Abstract:
PURPOSE: To provide, at a low cost, a MOS capacitor having such a small dependence on voltage of a capacitance value as allowing application thereof into an analog circuit, higher reliability and a small occupation area.
CONSTITUTION: A MOS capacitor comprises a P-type silicon substrate 1, an N-type impurity diffusion area 4 formed at a part of the silicon substrate 1 by introducing impurity, a silicon oxide film 5 formed on the impurity diffused area 4 and a polysilicon electrode 6 formed on the silicon oxide film 5. The N-type impurity diffused area 4 has the profile that concentration of impurity becomes higher toward the inside of the silicon substrate 1 from the interface with the silicon oxide film 5. Moreover, impurity concentration at the interface with the silicon oxide film 5 of the N-type impurity diffused area 4 is 1×1020cm-3 or less and peak position of the impurity concentration is deeper than 0.05μm which is the depth of the silicon oxide film 5 from the interface position. Accelerated oxidation at the time of thermal oxidation can be controlled and dependence on voltage of the capacitance value can also be controlled.
Inventors:
Chiaki Kudo
Akihiro Yamamoto
Akihiro Yamamoto
Application Number:
JP18894495A
Publication Date:
March 31, 2003
Filing Date:
July 25, 1995
Export Citation:
Assignee:
Matsushita Electric Industrial Co., Ltd
International Classes:
H01L27/04; H01L21/822; (IPC1-7): H01L21/822; H01L27/04
Domestic Patent References:
| JP63278328A | ||||
| JP61272963A | ||||
| JP2215152A |
Other References:
【文献】米国特許4877751(US,A)
Attorney, Agent or Firm:
Hiroshi Maeda (2 outside)
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