To provide a MOS current multiplying circuit by which ideal multiplication characteristics are obtained even when it is manufactured by using a normal manufacturing process.

A current square-law circuit 2A is formed by MOS transistors M3, M4 which are connected with each other by cascade and a MOS transistor M7 to form a current mirror circuit 11 with the MOS transistor M4. A current square-law circuit 2B is formed by MOS transistors M5, M6 which are connected with each other by cascade and a MOS transistor M8 to form a current mirror circuit 12 with the MOS transistor M6. The MOS transistors M4, M6 are connected with each other by diode. Constant voltage VB is impressed on gates of the MOS transistors M3, M5. The sum (Ix+Iy) and the difference (Ix-Iy) between first and second inputted current are supplied to sources of the MOS transistors M3, M5 respectively. Outputted current of the current square-law circuits 2A, 2B are subtracted by a current mirror circuit 13 and outputted current IOUT is obtained.