To suppress the capacitance of a capacitor to be provided in a multiplying circuit to multiply an analog signal value and a digital signal value as small when the circuit is defined, for example, as a semiconductor device constituted of a semiconductor thin film in the multiplying circuit.
In the multiplying circuit to multiply, for example, a digital signal value with (n) bits, (n) half-subtracters 1 to Hn to multiply the signal value in half are serially connected and the analog signal value A (IN) inputted in the half-subtracter H1 corresponding to the most significant bit digit is cumulatively multiplied by power of 1/2. Signal values inputted from the half- subtracters H1 to Hn corresponding to the switches are outputted when a value of an inputted control signal is '1' at respective (n) switches S1 to Sn which are provided in parallel. Respective bit values Dn to D1 from the most significant bit digit to the least significant bit digit of the digital signal value as a multiplying object are inputted as the control signals of the respective switches S1 to Sn. A signal value A (OUT) is outputted by totaling the analog signal values outputted from the switches S1 to Sn in adders P1, P2.
| JPH03188583 | MATRIX MULTIPLICATION DEVICE AND ITS APPLICATION TO NEURON NETWORK |
| WO/1982/001253 | ELECTRONIC WATT/VAR TRANSDUCER |
| WO/2024/143223 | PRODUCT-SUM OPERATOR |
SATO OSAMU
TOHORI HIDENORI
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