Title:
MOS RANDAMUAKUSESUSHUSEKIKAIROMEMORISERU
Document Type and Number:
Japanese Patent JPS5165840
Kind Code:
A
Abstract:
A random access memory cell comprises three capacitance means and three field effect transistors. One capacitance means is a pseudo-transistor which is embodied in the cell to principally provide means for refreshing the cell. One transistor has an alterable threshold and is embodied in the cell to store information at "power down".
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Inventors:
ARUBAATO MARINASU SHAFUAA
Application Number:
JP11985275A
Publication Date:
June 07, 1976
Filing Date:
October 06, 1975
Export Citation:
Assignee:
NCR CO
International Classes:
G11C11/403; G11C11/41; G11C14/00; G11C16/04; (IPC1-7): G11C11/40