Title:
多層用基板の積層技術
Document Type and Number:
Japanese Patent JP2005520333
Kind Code:
A
Abstract:
The present invention provides a number of techniques for laminating and interconnecting multiple substrates to form a multilayer package or other circuit component. A solder bump may be formed on the conductive pad of at least one of two or more substrates. The solder bump preferably is formed from an application of solder paste to the conductive pad(s). Adhesive films may be positioned between the surfaces of the substrates having the conductive pads, where the adhesive films include apertures located substantially over the conductive pads such that the conductive pads and/or solder bumps confront each other through the aperture. The two or more substrates then may be pressed together to mechanically bond the two or more substrates via the adhesive films. The solder bump(s) may be reflowed during or after the lamination to create a solder segment that provides an electrical connection between the conductive pads through the aperture in the adhesive films.
Inventors:
Pie, Dipaku Kay
Denny, Ronald Earl
Denny, Ronald Earl
Application Number:
JP2003576185A
Publication Date:
July 07, 2005
Filing Date:
March 14, 2003
Export Citation:
Assignee:
General Dynamics Advanced Information Systems, Inc.
International Classes:
H05K1/14; H01L23/12; H05K3/36; H05K3/46; H05K3/28; H05K3/34; (IPC1-7): H01L23/12; H05K1/14; H05K3/36; H05K3/46
Attorney, Agent or Firm:
Masahisa Takahashi
Hisamaru Hanada
Hisamaru Hanada