PURPOSE: To constitute a multi-output delay circuit by a circuit consisting of the small number of memory elements.

CONSTITUTION: A selector 10 of one input and four outputs and the write addresses of m/4 word RAMs 1 to 4 are controlled by a control circuit 100. Then data ah, ah+1, ah+2, ah+3 (h=4's multiple) stored in the RAMs 1 to 4 are read out by controlling read addresses and outputted from output terminals 00 to 03 through a crossbar switch 5 and plural unit delay elements 30 to 35, i.e., delayed by several cycles, to attain 4 (= n) output delay circuit.