Title:
BURN-IN STRESS ADDING AND SIMULTANEOUS TESTING METHOD AND DEVICE FOR MULTICHIP MODULE
Document Type and Number:
Japanese Patent JP3183825
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide various novel burn-in stress adding and testing methods for evaluating a multichip-module.
SOLUTION: A method of testing a multichip module having a plurality of semiconductor chips consists of a step of connecting a conductive test pattern 44, including provisional mutual connecting wiring to a multichip module 40 and connecting at least several semiconductor chips 30 in the multichip module 40 electrically to one another to facilitate these tests, a step of testing at least several semiconductor chips 30 in the multichip module 40 electrically at the same time using provisional mutual connecting wiring, and a step of removing the provisional mutual connecting wiring from the multichip module 40 after the simultaneous electrical test step.
Inventors:
Kenneth Edward Beilstein, Jr.
Claude Luis Burchin
Dennis Charles Dubois
Wayne John Howell
Gordon Arthur Kelly, Jr.
Christopher Paul Miller
David Jacob Perlman
Gustav Schlot
Edmund Julis Sproggis
Jody John Van Horn
Claude Luis Burchin
Dennis Charles Dubois
Wayne John Howell
Gordon Arthur Kelly, Jr.
Christopher Paul Miller
David Jacob Perlman
Gustav Schlot
Edmund Julis Sproggis
Jody John Van Horn
Application Number:
JP13524196A
Publication Date:
July 09, 2001
Filing Date:
May 29, 1996
Export Citation:
Assignee:
International Business Machines Corporation
International Classes:
G01R31/26; G01R1/04; G01R31/28; H01L21/66; H01L25/00; (IPC1-7): G01R31/26; H01L21/66
Domestic Patent References:
| JP755878A | ||||
| JP6510122A |
Attorney, Agent or Firm:
Hiroshi Sakaguchi (1 person outside)