PURPOSE: To simplify a timing circuit by equalizing the orders and the timings in respect to address signals of a ROM, where coefficients are stored, gate control signals of registers and delay equipments, and start signals of a multiplier.

CONSTITUTION: Register 7 and delay equipments 81∼84 constitute the first circular digital filter, and register 12 and delay equipments 131∼134 constitute the second circular digital filter. By output signals of binary counter 4 which is operated synchronously with signals applied to input terminal 2, the register and delay equipments of the first or the second circular digital filter are designated successively to output digital signals successively. This output is supplied to multiplier 9 and is multiplied by a coefficient stored in ROM 6, and after that, the output is added to the signal from register 1, and the result is outputted from output terminal 15.