Title:
MULTIPLEX RESONANCE TUNNEL EFFECT CIRCUIT FOR DIGIT MULTILEVEL LOGIC OPERATION WITH CODE
Document Type and Number:
Japanese Patent JP3724825
Kind Code:
B2
Abstract:
PURPOSE: To provide a device for a resonance tunnel effect device, which can execute a multilevel logical operation, instead of a conventional binary operation circuit for realizing the multilevel logical operation integrated circuit of high density and extreme high efficiency.
CONSTITUTION: An adder for calculating the sum of two numbers shown by the words of digit range 3 base 4 with code is constituted of an addition circuit 40 generating a digit sum Si by adding the corresponding digits of input words X and Y, a converter circuit 42 from a range 5 with code for analyzing the sum of digits into an intermediate sum and a carry digit by using a multilevel folding circuit connecting voltage dividers into a range 3 with the code and the two sets of the addition circuits 40 adding the intermediate sum and the carry digit and generating the digit of a result. It is preferable to show the sum by the word of the digit range 3 base 4 with the code, and the multilevel circuit contains the resonance tunnel effect transistor.
Inventors:
Albert Eich. Taddyken
Lutz Jay Mitchell
Lutz Jay Mitchell
Application Number:
JP14524594A
Publication Date:
December 07, 2005
Filing Date:
May 24, 1994
Export Citation:
Assignee:
Texas Instruments Incorporated
International Classes:
G06G7/14; G06F7/49; G06F7/503; H03K19/10; H03K19/20; (IPC1-7): G06G7/14; G06F7/49; H03K19/10; H03K19/20
Domestic Patent References:
| JP63216131A | ||||
| JP2113494A | ||||
| JP1213716A |
Attorney, Agent or Firm:
Hideto Asamura
Hajime Asamura
Hayashi Zouzo
Kuniaki Shimizu
Hajime Asamura
Hayashi Zouzo
Kuniaki Shimizu