Title:
MULTIPLICATION CIRCUIT AND FILTER CIRCUIT
Document Type and Number:
Japanese Patent JP3537739
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a multiplication circuit which has a small scale and small power consumption and is suitable to the digital multiplication by performing the weighted addition by means of a feedback capacitance connected to an amplifier circuit in terms of negative feedback or a register and outputting the result of multiplication as analog voltage.
SOLUTION: The outputs of an MUX91, an SEL91, an MUX92, an SEL92, an SEL93 and an MUX93 are connected to the capacitance C91 to C96 respectively. The output of capacitances C91 to C96 are integrated and inputted to the inverted input of an operational amplifier AMP9. Each of capacitances C91 to C96 has its capacity that is proportional to the sum of weight of input bits of every AND the sum total of these capacities is calculated to obtain the result of multiplication. Then a switch SW91 is closed and a switch SW92 is connected to a non-inverted input for refreshing the capacitances C91 to C96. In other words, this multiplication circuit is suitable to the digital multiplication since the circuit outputs the result of multiplication as analog voltage.
More Like This:
Inventors:
Shu, Nagaaki
Application Number:
JP2000196629A
Publication Date:
June 14, 2004
Filing Date:
December 14, 1998
Export Citation:
Assignee:
YOZAN INC
International Classes:
G06G7/16; H03H11/04; H03H11/12; (IPC1-7): G06G7/16; H03H11/04; H03H11/12