To provide a MOS multiplication circuit which reduces influence due to the reduction of the mobility of transistor carrier and is suitable to be formed on a semiconductor integrated circuit and a MOS-OTS (operational transconductance amplifier).

The circuit includes 1st to 4th transistors where fixed voltage is applied between their gates and whose sources are connected in a common way and which are driven by a constant current source and operate in a linear area. When a 1st input voltage is defined as V1, a 2nd input voltage is defined as V2, V3 is defined as an optional voltage and (a), (b) and (c) are defined as optional constants, aV1+bV2+V3, (a-c)V1+bV2+V3, aV1+(b-1/c)V2+V3 and (a-c)V1+(b-1/c)V2+V3 voltages are applied to the drains of the 1st to 4th transistors, respectively, the 1st to 4th transistors operate in the linear area, the difference current between the sum current of drain currents of the 1st and 4th transistors and the sum current of drain currents of the 2nd and 3rd transistors is defined as an output current, and current that is in proportion to the product of a 1st input voltage and a 2nd input voltage is outputted.