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Title:
MULTIPLICATION CIRCUIT
Document Type and Number:
Japanese Patent JPS54118756
Kind Code:
A
Abstract:

PURPOSE: To ensure the offset for the nonlinearity error for two units of the transconductance by giving the parallel connection to one side of the input terminal and then giving subtraction to two units of the output given in the different polarities for the other side.

CONSTITUTION: Transconductance operational amplifier 3 and 4, which feature the same linearity error of conductance, are selected. The multiplication output of the input of amplifier 3 and bias input 2 given via positive-negative converter 5 is supplied to operational amplifier 6 along with the multiplication output of the input of amplifier 4 and bias input 2. And the signal output obtained by reversing the multiplication output of amplifier 3 is delivered through terminal 7 along with the multiplication output of amplifier 4 which received addition via amplifier 6. Thus, the error can be offset by adding the input the error directions of which are quite opposite to each other through amplifier 6, and accordingly the error caused by the nonlinearity of the transconductance amplifier can be reduced.


Inventors:
KAWAMURA SHIGENORI
KIKUCHI TOMOHIKO
Application Number:
JP2541378A
Publication Date:
September 14, 1979
Filing Date:
March 08, 1978
Export Citation:
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Assignee:
HITACHI ELECTRONICS
International Classes:
G06G7/163; (IPC1-7): G06G7/163



 
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