Title:
MULTIPLIER CIRCUIT
Document Type and Number:
Japanese Patent JP3230702
Kind Code:
B2
Abstract:
PURPOSE: To reduce considerably quadrature distortion at the time of demodulation, carrier leakage and waveform distortion in the multiplier circuit.
CONSTITUTION: A 1st differential input signal is inputted to 1st and 2nd differential input stages, and a couple of differential output signals whose phases are inverted to each other outputted from 2nd and 4th transistors (TRs) whose bases imaginarily connect to ground in terms of AC are inputted to a multiplier section. It is prevented that a 1st differential input signal is leaked to the multiplier section via a parasitic capacitance of the 2nd and 4th TRs and also it is prevented that a 2nd differential input signal is leaked to the signal source of the 1st differential input signal via a parasitic capacitance. Thus, the differential amplifier circuit is realized, in which quadrature distortion when a 1st differential input signal is demodulated, leakage of a 2nd differential input signal and waveform distortion are considerably reduced.
Inventors:
Yasuaki Ishii
Nobuhisa Ozawa
Nobuhisa Ozawa
Application Number:
JP36061392A
Publication Date:
November 19, 2001
Filing Date:
December 31, 1992
Export Citation:
Assignee:
ソニー株式会社
International Classes:
H03D1/04; G06G7/163; H03D1/18; H03D7/14; (IPC1-7): H03D1/18; G06G7/163; H03D1/04; H03D7/14
Domestic Patent References:
| JP6111037A | ||||
| JP63159986A |
Attorney, Agent or Firm:
Keiki Tanabe