Title:
MULTIPLIER
Document Type and Number:
Japanese Patent JP3578136
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To solve problems that the circuit scale gets large and that electric power consumption increases, because a complicated correction circuit is required to be added in an output part or the like to compensate fluctuation of a bias voltage or the like, in a conventional multiplier using an MOS transistor.
SOLUTION: This multiplier has NMOS transistors 3, 4, 5, and constant- voltage sources 6, 9, 12 connected respectively to gates of the NMOS transistors 3, 4, 5. In the multiplier, a voltage value in the constant-voltage source 9 is made equal to a voltage value in the constant-voltage source 12, and the NMOS transistor 4 and the NMOS transistor 5 are formed to be mutually the same.
Inventors:
Atsushi Hirabayashi
Kenji Komori
Kenji Komori
Application Number:
JP2001391355A
Publication Date:
October 20, 2004
Filing Date:
December 25, 2001
Export Citation:
Assignee:
ソニー株式会社
International Classes:
G06G7/16; G06G7/163; G06G7/12; G06G7/164; H03F3/45; (IPC1-7): G06G7/16; H03F3/45
Domestic Patent References:
| JP5046792A | ||||
| JP8050625A |
Attorney, Agent or Firm:
Akira Koike
Eiichi Tamura
Seiji Iga
Eiichi Tamura
Seiji Iga
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