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Patent Searching and Data


Title:
MOS/BIMOS MULTIPLIER
Document Type and Number:
Japanese Patent JPH11250167
Kind Code:
A
Abstract:

To provide a highy practical multiplier that can be realized on semiconductor integrated circuit.

In addition to MOSFETs M1 to M3 to be respectively driven by constant current sources 4 to 6, this multiplier is provided with a MOSFET M4 to operate in a linear area with its drain connected to the source of the MOSFET M1, its source connected to the source of the MOSFET M2 and a MOSFET M5 to operate in a linear area with its drain connected to the source of the MOSFET M3, its source connected to the source of the MOSFET M2. Input voltage V1 is impressed to the common connected gate of the MOSFETs M1, M3 and input voltage V2 is impressed to the gate of the MOSFET M2. Input voltage V3, V4 are respectively impressed to the gates of the MOSFETs M4, M5. A difference berween currents allowed to flow into respective MOSFETs M4, M5 includes the multiplied result of (V1-V2) and (V3-V4).


Inventors:
KIMURA KATSUHARU
Application Number:
JP4606298A
Publication Date:
September 17, 1999
Filing Date:
February 26, 1998
Export Citation:
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Assignee:
NEC CORP
International Classes:
G06G7/163; (IPC1-7): G06G7/163
Attorney, Agent or Firm:
Izumi Katsufumi