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Title:
SQUARE NUMBER CALCULATION CIRCUIT, COMPOSITE DEFERENTIAL AMPLIFIER CIRCUIT AND MULTIPLIER USING THESE CIRCUITS
Document Type and Number:
Japanese Patent JPH11250168
Kind Code:
A
Abstract:

To provide a square number calculation circuit having a square characteristic over the whole operation input voltage range that can be realized on a semiconductor integrated circuit.

A MOS differential pair is formed by MOS transistors(TRs) M1, M2 of which sources are mutually connected. Input voltage V1 is impressed between the gates of the TRs M1, M2. MOS TRs M3, M4 are respectively connected to the TRs M1, M2 as their loads. A tripple tail cell is formed by a constant current source 1 and MOS TRs M5 to M7 of which sources are mutually connected. Constant voltage Vc is impressed to the gate of the TR M7. Two output voltages V01, V02 from the MOS differential pair are respectively impressed to the gates of the TRs M5, M6. A 1st output current I+ is taken out from the drain of the TR M7 and a 2nd output current I is taken out from the drains of the TRs M5, M6.


Inventors:
KIMURA KATSUHARU
Application Number:
JP5247498A
Publication Date:
September 17, 1999
Filing Date:
March 04, 1998
Export Citation:
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Assignee:
NEC CORP
International Classes:
G06G7/20; G06G7/16; (IPC1-7): G06G7/20; G06G7/16
Attorney, Agent or Firm:
Izumi Katsufumi