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Patent Searching and Data


Title:
積和演算装置
Document Type and Number:
Japanese Patent JP6876220
Kind Code:
B2
Abstract:
In each of analog circuits 11 in a multiply-accumulate operation device 10, electric charges, each of the electric charges having a size depending on each of values of N+ electric signals and each of values of positive loads corresponding to the N+ electric signals, are held in a first capture-and-storage means 19, electric charges, each of the electric charges having a size depending on each of values of (N-N+) electric signals and each of absolute values of negative loads corresponding to the (N-N+) electric signals, are held in a second capture-and-storage means 27, a sum of N+ multiplied values obtained by multiplying each of the positive loads corresponding to the N+ electric signals by each of the values of the N+ electric signals respectively is calculated when detecting that a voltage held in the first capture-and-storage means 19 reaches a first threshold, a sum of (N-N+) multiplied values obtained by multiplying each of the absolute values of the negative loads corresponding to the (N-N+) electric signals by each of the values of the (N-N+) electric signals respectively is calculated when detecting that a voltage held in the second capture-and-storage means 27 reaches a second threshold, and a sum of N multiplied values is obtained by subtracting the sum of (N-N+) multiplied values from the sum of N+ multiplied values.

Inventors:
Takashi Morie
Kingship
Tamu right
Application Number:
JP2018534339A
Publication Date:
May 26, 2021
Filing Date:
August 03, 2017
Export Citation:
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Assignee:
Sony Group Corporation
International Classes:
G06G7/12; G06G7/60; G06N3/063
Domestic Patent References:
JP2004110421A
JP201699707A
Foreign References:
US20050160130
Attorney, Agent or Firm:
Junichi Omori
Mitsuru Takahashi
Teppei Nakamura
Ori Akira
Masayoshi Sekine
Ayako Kaneko
Shintaro Kanayama
Chiba Ayako
Shiraka Tomohisa