To prevent the occurrence of an operation error occurred by means of the output of an odd stage by connecting a plurality of neuro-amplifier circuits inverting and outputting input voltage in series, generating compensation voltage similar to refresh voltage outputted at the time of refreshing a neuro- amplifier and reducing compensation voltage from the output of the odd neuro- amplifier circuit.
The three stages of neuro-amplifier circuits 22 are connected in series. Refresh reference voltage VREF is inputted to the neuro-amplifier circuits 22 of first and third stages. Then, input voltage AIN is inputted to the neuro-amplifier circuit 22 of the first stage. Inverters contained in the respective neuro-amplifier circuits 22 generate errors owing to the manufacture fluctuation of semiconductor devices and a temperature. A compensation voltage generation circuit 40 also outputs compensation voltage which is almost similar to the actual output voltage Vro of the neuro-amplifier circuit 22 at the time of refreshing.
HIGUCHI HIROSHI
SHU NAGAAKI
TAKATORI IKUEIKAI KK