Title:
PHASE COMPARING DEVICE AND SIGNAL DELAY CIRCUIT
Document Type and Number:
Japanese Patent JPH11355111
Kind Code:
A
Abstract:
To obtain an output signal without including a phase noise component by cancelling the leak of a clock signal which is demodulated by means of a data signal in a phase comparing device.
Sample-and-hold circuits 3 and 4 are triggered by the rising and falling of a data positive phase input signals and a synthesizing circuit 5 is triggered by the output signal of a data delay circuit 6 having a delay being equal to the one which occurs in outputs from the sample-and-hole circuits 3 and 4. Thus, only a DC voltage of a state where the sample-and-hold circuit 3 and 4 are held is selected in the synthesizing circuit 5 and the unnecessary leak of the clock signal to the output of the phase comparing device is cancelled.
Inventors:
CHIBA HIROYUKI
TAKEYARI RYOJI
ISHIKAWA KYOSUKE
TAKEYARI RYOJI
ISHIKAWA KYOSUKE
Application Number:
JP16179798A
Publication Date:
December 24, 1999
Filing Date:
June 10, 1998
Export Citation:
Assignee:
HITACHI LTD
International Classes:
H03K5/13; H03K5/26; H03L7/091; (IPC1-7): H03K5/26; H03K5/13; H03L7/091
Attorney, Agent or Firm:
Ogawa Katsuo