PURPOSE: To increase the operation speed by determining a path only with value comparison without requiring the just preceding metric in the metric operation which obtains the path.

CONSTITUTION: A comparator 1 which receives an input Xn and compares and collates the value of the input Xn with a prescribed value to output a comparison 1 output 102, a comparator 2 which receives the input Xn and compares and collates the value of the input Xn with a prescribed value to output a comparison 2 output 103, an OR circuit 4 which takes the comparison 1 output 102 and the comparison 2 output 103 as the input to output decoded data 104, a metric unit 3 which calculates and outputs a metric 105 in accordance with the input Xn and a prescribed arithmetic formula, a control signal generator 5 which generates and outputs a prescribed load signal 107 and a reset signal 108, a maximum detector 6 which generates and outputs a ring counter reset signal 106, and a shift register 7 which shifts and outputs the decoded data 104 are provided to constitute a maximum likelihood decoder.