Title:
【発明の名称】半導体集積回路
Document Type and Number:
Japanese Patent JP2519580
Kind Code:
B2
Abstract:
A self-timed random-access memory device includes randomly accessible memory circuitry (7), a clock generator (9) responsive to an external clock signal for generating an internal clock signal, an input circuit (8') responsive to the internal clock signal for latching and outputting a supplied input signal, an output circuit (11') responsive to the internal clock signal for latching and outputting an output from the memory device, and circuitry (81, 82, 85, 86; 115, 116, 124, 125; 135, 136, 144, 145) responsive to a through state specifying signal (TH, THM) for disabling the latch function of the input circuit and the output circuit. The memory device can be switched, in response to the through state specifying signal, between a mode operating synchronously with the externally supplied clock signal and another mode operating asynchronously with the externally supplied clock signal.
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Inventors:
SHIOMI TOORU
OOHAYASHI SHIGEKI
OOBA ATSUSHI
OOHAYASHI SHIGEKI
OOBA ATSUSHI
Application Number:
JP16084790A
Publication Date:
July 31, 1996
Filing Date:
June 19, 1990
Export Citation:
Assignee:
MITSUBISHI ELECTRIC CORP
International Classes:
G11C11/414; G11C7/10; G11C7/22; (IPC1-7): G11C11/414
Attorney, Agent or Firm:
Fukami Hisaro (2 outside)