PURPOSE: To generate a synchronization clock synchronously with a frequency of a transmission speed of reception data at a fast lock time with no adjustment.

CONSTITUTION: A synchronization pulse generating circuit 3 generates synchronization pulses f, g, h based on reception data R×D (or a) and a level detection circuit 4 generates a level signal (k). A delimiter detection circuit 5 generates a high level signal (m) and a low level signal (l) based on the synchronization pulse (h) and the level signal (k), and a synchronization pulse generating circuit 6 of a delimiter section generates a synchronization pulse signal (p) based on the low level signal (l). Thus, a selector circuit 7 based on the high low level signals (m), (l) implements masking and synthesis of the synchronization pulse (f) and the synchronization pulse (p) and extracts and outputs a synchronization clock R×CC from the reception data R×D.