NEURAL CIRCUIT IMITATION ELEMENT - 株式会社リコー

Title:

NEURAL CIRCUIT IMITATION ELEMENT

Document Type and Number:

Japanese Patent JP3463890

Kind Code:

B2

Abstract:

PURPOSE: To realize various kinds of combined configuration of an offset input introducing system with a system where the value of a connection coefficient is preserved by a binary number, converted into a pulse string and supplied to an operation without enlarging a circuit scale.
CONSTITUTION: A random number by a second random number generating circuit consisting of a linear feed-back shift register 17 which is provided in respective neurons or the previously fixed bit of a shift register 21 with the output of the linear feed-back shift register 17 constituting the second random number generating circuit as an input is commonly utilized for generating the offset input pulse string in the neuron and for selecting the generation polynomial of the first random number generating circuit in a synapse.

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Inventors:

Toshiyuki Furuta
Shuji Motomura

Application Number:

JP8463894A

Publication Date:

November 05, 2003

Filing Date:

April 22, 1994

Export Citation:

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Assignee:

株式会社リコー

International Classes:

G06G7/60; G06F15/18; G06N3/06; (IPC1-7): G06G7/60; G06N3/06

Domestic Patent References:

JP520292A
JP7334478A

Other References:

江口裕俊、他，学習機能を有するパルス密度型ニューロンモデルとそのハード化，電子情報通信学会技術研究報告，日本，社団法人電子情報通信学会，１９９０年１０月２５日，Ｖｏｌ．９０，Ｎｏ．２７３，ｐ．６３−７０

Attorney, Agent or Firm:

Akira Kashiwagi (1 person outside)

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