Title:
半導体記憶素子を用いたニューラルネットワーク演算回路及び動作方法
Document Type and Number:
Japanese Patent JP6844013
Kind Code:
B2
Abstract:
Connection weight coefficients to be used in a neural network computation are stored in a memory array (20). A word line drive circuit (24) drives a word line (22) corresponding to input data of a neural network. A column selection circuit (25) connects to a computation circuit (26) bit lines to which a connection weight coefficient to be computed is connected. The computation circuit (26) determines the sum of cell currents flowing in the bit lines (23). A result of the determination made by the computation circuit (26) is stored in an output holding circuit (27), and is set as an input of a neural network in the next layer, to the word line drive circuit (24). A control circuit (29) instructs the word line drive circuit (24) and the column selection circuit (25) to select the word line (22) and the bit line (23) to be used in the neural network computation, based on information held in a network configuration information holding circuit (28).
Inventors:
Yuriko Hayata
Kazuyuki Kono
Masayoshi Nakayama
Reiji Mochida
Takashi Ono
Hitoshi Suwa
Kazuyuki Kono
Masayoshi Nakayama
Reiji Mochida
Takashi Ono
Hitoshi Suwa
Application Number:
JP2019540878A
Publication Date:
March 17, 2021
Filing Date:
August 24, 2018
Export Citation:
Assignee:
Panasonic Corporation
International Classes:
G06N3/063; G06G7/60; G11C11/54
Domestic Patent References:
| JP628331A | ||||
| JP4054685A | ||||
| JP5282269A |
Foreign References:
| US5371834 |
Attorney, Agent or Firm:
Hiromori Arai
Eisaku Teratani
Shinichi Michisaka
Eisaku Teratani
Shinichi Michisaka