Title:
NEURO CHIP
Document Type and Number:
Japanese Patent JP3246764
Kind Code:
B2
Abstract:
PURPOSE: To improve reliability and to accelerate speed by economizing the capacity of a memory to be used for performing neuron arithmetic, and reducing the error or delay of data read and write.
CONSTITUTION: A memory interface circuit is provided with an address generator 12 to read and write data at a corresponding address position on a memory 18 by generating a pointer by the address generating means 12 as the pointer of the next data, comparator 15 to judge coincidence or non-coincidence by comparing the value of the pointer stored in the storage means 13 with the value of a pointer counter 14 to repeat count-up, data selection means 17 to read fixed value data when both of values are not coincident as the discriminated result of the comparative discriminating means 15 or to read the next data from the memory when they are coincident.
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Inventors:
Katsuichi Shimokawa
Narihiko Aramaki
Narihiko Aramaki
Application Number:
JP11763792A
Publication Date:
January 15, 2002
Filing Date:
May 11, 1992
Export Citation:
Assignee:
Toshiba Corporation
International Classes:
G06F15/18; G06F17/16; G06G7/60; G06N3/063; G06N99/00; (IPC1-7): G06N3/063; G06F17/16
Domestic Patent References:
| JP3251947A | ||||
| JP5165844A | ||||
| JP2273867A | ||||
| JP6293738A | ||||
| JP36548B2 |
Other References:
下川勝千、他２名，”デジタルニューロコンピュータ ＭＵＬＴＩ ＮＥＵＲＯ”，東芝レビュー，株式会社東芝，１９９１年１２月，ＶＯＬ．４６，ＮＯ．１２，Ｐ．９３１−９３４
Attorney, Agent or Firm:
Hideaki Togawa