Title:
NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURE THEREOF
Document Type and Number:
Japanese Patent JP3389003
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To restrain a short channel effect and improve punch through breakdown strength in a non-volatile semiconductor memory device.
SOLUTION: This device has a tunnel oxide film 102 formed on a silicon substrate 101, a floating gate electrode 103 formed on the tunnel oxide film 102, an ONO film 104 formed on the floating gate electrode 103, and a control gate electrode 105 formed on the ONO film 104. The device also has source/ drain 109, 106 formed in the silicon substrate 101 on both sides of the control gate electrode 105. In this case, a diffusion layer 107 containing baron is provided only in a part near the drain in the silicon substrate 101 directly under the floating gate electrode 103. In addition, a diffusion layer 108 containing arsenic to be a part of the drain 109 is provided under the diffusion layer 107 containing boron. This diffusion layer 108 is formed in contact with the drain 109.
Inventors:
Fumitaka Sugaya
Application Number:
JP16106396A
Publication Date:
March 24, 2003
Filing Date:
May 31, 1996
Export Citation:
Assignee:
Nippon Steel Corporation
International Classes:
H01L21/8247; H01L21/205; H01L21/265; H01L27/115; H01L29/788; H01L29/792; (IPC1-7): H01L21/8247; H01L21/205; H01L21/265; H01L27/115; H01L29/788; H01L29/792
Domestic Patent References:
| JP677499A | ||||
| JP509388A |
Attorney, Agent or Firm:
Koetsu Kokubun
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