Title:
NON-VOLATILE SEMICONDUCTOR MEMORY AND METHOD FOR USING IT
Document Type and Number:
Japanese Patent JP3103457
Kind Code:
B2
Abstract:
PURPOSE: To increase storage capacity of a EPROM.
CONSTITUTION: Staircase voltage of which a level varies in staircase state such as 10V, 11V, 12V... from 0V for every 1 ms is generated by a variable voltage generation circuit 6, and this staircase voltage is applied to a control gate of the prescribed memory cell through a word line in which a memory cell array 1 is selected. And voltage of 8.5V is applied to a selected bit line for 0.8 ms from a pulse generation circuit 7 matching with timing in which voltage of a desired level is applied, a hot electron is injected to a floating gate of the memory cell and a threshold value of the memory cell is varied. Variation states of this threshold value are respectively assumed to states of '01', '10', '11' in accordance with voltage level of staircase voltage, and a state in which nothing is written in the memory cell is assumed to a state of '00'. Thereby, data of four values can be stored in one memory cell.
Inventors:
Toshio Wada
Kenji Anzai
Shoichi Iwasa
Yasuo Sato
Yuichi Egawa
Kenji Anzai
Shoichi Iwasa
Yasuo Sato
Yuichi Egawa
Application Number:
JP8006893A
Publication Date:
October 30, 2000
Filing Date:
March 15, 1993
Export Citation:
Assignee:
Nippon Steel Corporation
International Classes:
G11C17/00; G11C11/56; G11C16/02; G11C27/00; H01L21/8247; H01L27/115; (IPC1-7): G11C16/02; H01L27/115
Domestic Patent References:
| JP3237692A | ||||
| JP626493A | ||||
| JP62257699A |
Attorney, Agent or Firm:
Koetsu Kokubun