Title:
不揮発性半導体記憶装置
Document Type and Number:
Japanese Patent JP4177847
Kind Code:
B2
Abstract:
A nonvolatile semiconductor memory device is provided with a memory cell array, a judgment potential correction circuit, and a readout circuit. In the memory cell array, a plurality of memory cells are arranged in a matrix form, and the array includes a first memory cell as a readout object and a second memory cell disposed adjacent to the first memory cell. The judgment potential correction circuit corrects a judgment potential based on a threshold value of the second memory cell. The readout circuit reads the first memory cell as the readout object by use of the corrected judgment potential.
Inventors:
Atsushi Sato
Keiji Suto
Fumitaka Arai
Keiji Suto
Fumitaka Arai
Application Number:
JP2006001456A
Publication Date:
November 05, 2008
Filing Date:
January 06, 2006
Export Citation:
Assignee:
Toshiba Corporation
International Classes:
G11C16/02; G11C16/04
Domestic Patent References:
| JP2002324400A | ||||
| JP2004326866A | ||||
| JP2005538485A | ||||
| JP2007519162A | ||||
| JP2003249085A | ||||
| JP2004192789A |
Foreign References:
| US5867429 |
Attorney, Agent or Firm:
Takehiko Suzue
Satoshi Kono
Makoto Nakamura
Kurata Masatoshi
Takashi Mine
Yoshihiro Fukuhara
Sadao Muramatsu
Ryo Hashimoto
Satoshi Kono
Makoto Nakamura
Kurata Masatoshi
Takashi Mine
Yoshihiro Fukuhara
Sadao Muramatsu
Ryo Hashimoto