Title:
NONLINEAR ARITHMETIC UNIT AND NEURAL NETWORK
Document Type and Number:
Japanese Patent JP3644144
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To make the circuit of the nonlinear arithmetic unit simple and high in precision.
SOLUTION: The nonlinear arithmetic unit is constituted by connecting dummy NPN bipolar transistors each consisting of a MOS operational amplifier 10, an NMOS transistor 12, and a diode 14. The output terminal of the operational amplifier 10 is connected to the gate of the transistor 12, and the source of the transistor 12 and a substrate are connected to the anode of the diode 14 and further connected to the inverted input terminal of the operational amplifier 10. The terminal voltage across the diode 14 is negatively fed from the output terminal of the operational amplifier 10 back to the inverted input terminal of the operational amplifier 10 through the transistor 12 and the drain current increases in proportion to exp 'base potential', so the dummy NPN bipolar transistor is constituted which includes the uninverted input terminal of the operational amplifier 10 as its base, the drain of the transistor 12 as its collector, and the cathode of the diode 14 as its emitter.
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Inventors:
Kiichi Yamada
Shuho Ikeda
Kazumasa Murai
Shuho Ikeda
Kazumasa Murai
Application Number:
JP21026796A
Publication Date:
April 27, 2005
Filing Date:
August 08, 1996
Export Citation:
Assignee:
Fuji Xerox Co., Ltd
International Classes:
G06G7/60; G06F15/18; G06N3/06; (IPC1-7): G06G7/60; G06N3/06
Domestic Patent References:
| JP61131073A | ||||
| JP4289592A | ||||
| JP6309477A |
Attorney, Agent or Firm:
Atsushi Nakajima
Kato Kazunori
Katsuichi Nishimoto
Hiroshi Fukuda
Kato Kazunori
Katsuichi Nishimoto
Hiroshi Fukuda